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tm
TE CH
T15V256A
SRAM
FEATURES
* High speed access time: 50/70/85/100ns * Power supply current : Operating :35mA(max) Standby : 5uA * Power supply : 2.7V to 3.6V * Fully static operation - No clock or refreshing required * All inputs and outputs directly LVTTL compatible * Common I/O capability * Data retention voltage : 1.5V (min) * Available packages :28-pin SOP ,TSOP-I (8x13.4mm forward type and reverse type). * Operating temperature : 0 ~ +70 C -40 ~ +85 C
32K X 8 LOW POWER CMOS STATIC RAM
GENERAL DESCRIPTION
The T15V256A is a low power and low voltage CMOS static RAM. organized as 32,768 x 8 bits that operates on a 2.7V to 3.6V power supply. Data retention is guaranteed at a power supply voltage as low as 1.5V. This device is packaged in a standard 28-pin SOP or TSOP-I forward and reverse type.
BLOCK DIAGRAM
Vcc
Vss
A0 A14 CS OE WE I / O1
CONTROL
. .
PART NUMBER EXAMPLES
PART NO. T15V256A-70D T15V256A-85P T15V256A-85R PACKAGE CODE
D=SOP P= TSOP-I(Forward) R= TSOP-I(Reverse) 0 ~ +70 C
. . .
DECODER
CORE ARRAY
Operating
Temperature
DATA I/O
I / O8
T15V256A-70DI T15V256A-85PI T15V256A-85RI
D=SOP P= TSOP-I(Forward) R= TSOP-I(Reverse) -40 ~ +85 C
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 1
Publication Date: SEP. 2001 Revision:A
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A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14
TE CH
T15V256A
PIN CONFIGURATION (Top View)
28 27 26 25 24 23 Vcc WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
SOP
22 21 20 19 18 17 16 15
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10
TSOP-I Forward
TSOP-I Reverse
PIN DESCRIPTION
SYMBOL A0 - A14 I/O1 - I/O8
CS
WE OE
Vcc Vss
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 2
Publication Date: SEP. 2001 Revision:A
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TE CH
T15V256A
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Vss Potential Inputs to Vss Potential Power Dissipation Storage Temperature RATING -0.5 to + 4.6 -0.5 to Vcc +0.5 0.7 -60 to +150 UNIT V V W C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN 2.7 -0.3 2.4 0/-40 TYP MAX 3.6 0.6 Vcc+0.3 +75/+85 UNIT V V V C
VIL VIH TA
TRUTH TABLE
CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1- I/O8 High-Z High-Z Data Out Data In Power Standby Active Active Active
OPERATING CHARACTERISTICS
(Vcc = 2.7V to 3.6V, Vss = 0V, Ta = 0 ~ +70 C /-40 to 85C)
PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. TEST CONDITIONS Vin=Vss to Vcc VI/O=Vss to Vcc ,
OE =
I LI I LO VOL VOH
Icc
MIN. TYP. MAX. UNIT 1 A 2.2 1 0.4 35 30 25 20 0.3 5 A V V mA mA mA mA mA uA
VIH
CS =VIH or or WE = VIL
I OL = + 2.1mA I OH = - 1.0mA CS =VIL , I/O=0mA
Cycle = MIN. Duty = 100%
-50 -70 -85 -100
I SB I SB1
CS =VIH , Cycle=min, Duty=100% CS Vcc-0.2V
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 3
Publication Date: SEP. 2001 Revision:A
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TE CH
T15V256A
CAPACITANCE
(Vcc = 2.7V to 3.6V, Ta = 25C, f = 1 MHz)
PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT= 0V MAX. 6 8 UNIT pF pF
CIN CI/O
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0.6V to 2.4V 3 ns 1.4V See Fig. 1,2
AC TEST LOADS AND WAVEFORM
3.0V OUTPUT
R1 - 1210 ohm
3.0V OUTPUT
R1- 1210 ohm
30pF Including Jig and Scope
R2 1380 ohm
5pF Including Jig and Scope
R2 1380 ohm
(For TCLZ TOLZ TCHZ TOHZ TWHZ TOW ) , , , , ,
Fig 1
Fig 2
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 4
Publication Date: SEP. 2001 Revision:A
tm
TE CH
T15V256A
AC CHARACTERISTICS
(Vcc=2.7V to 3.6V, Vss = 0V, Ta = 0 ~ +70 C /-40 to 85C)
(1) READ CYCLE
PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address Change SYM.
-50ns
MIN MAX
-70ns
MIN. MAX.
-85ns
-100ns
UNIT
MIN. MAX. MIN. MAX.
tRC tAA tACS tAOE tCLZ* tOLZ* tOHZ* tOH
50 7 5 10
50 50 25 20 20 -
70 10 5 10
70 70 35 25 25 -
85 10 5 10
85 85 40 30 30 -
100 10 5 10
100 100 50 30 30 -
ns ns ns ns ns ns ns ns ns
Chip Deselection to Output in High Z tCHZ*
* These parameters are measured with 5pF test load.
(2)WRITE CYCLE
PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Active from End of Write SYM.
-50ns
MIN MAX
-70ns
-85ns
-100ns
MIN. MAX. MIN. MAX. MIN. MAX.
tW C tCW tAW tAS tWP tW R tDW tDH tWHZ* tOW
50 40 40 0 30 0 25 0 5
20 -
70 60 60 0 50 0 30 0 5
25 -
85 70 70 0 60 0 35 0 5
30 -
100 80 80 0 70 0 40 0 5
30 -
UNI T ns ns ns ns ns ns ns ns ns ns
* These parameters are measured with 5pF test load.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 5
Publication Date: SEP. 2001 Revision:A
tm
TE CH
T15V256A
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR Test Condition CS Vcc-0.2V
Vcc=3.0, CS Vcc-0.2V
Min 1.5 0 5
Typ -
max 3.6 5
unit V uA ms
tSDR tRDR
See data retention waveform
-
-
DATA RETENTION WAVE FORM
Data Retention Mode
V cc_typ VCC t SDR
V DR > 1.5V
t
Vcc_TYP RDR
CS V
IH
CS >VCC-0.2V
V
IH
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 6
Publication Date: SEP. 2001 Revision:A
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TE CH
T15V256A
TIMING WAVEFORMS READ CYCLE 1
(Address Controlled)
tR C
Address
tA A tOH tO H
DO U T
READ CYCLE 2
(Chip Select Controlled)
CS
tA C S tC L Z tC H Z
DOUT
READ CYCLE 3
(Output Enable Controlled)
tR C
A d dr es s
tA A
OE
tAOE tOLZ tO H
CS
tA CS tC LZ t OH Z tCHZ
DOUT
DO N'T CA RE UNDE FINE D
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 7
Publication Date: SEP. 2001 Revision:A
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Ad dr es s
TE CH (OE CLOCK)
tW C
T15V256A
WRITE CYCLE 1
t
WR
OE t CW
CS t t AW WP
WE t t AS O HZ ( 1, 4) D OUT t DW t DH
DI N
WRITE CYCLE 2
( OE = V
IL Fixed)
tWC
A ddress
tC W tWR
CS
tA W tW P
WE
tA S
tOH tW H Z (1, 4 ) tOW (2 ) (3 )
DOUT
tDW tDH
D IN
DO N' T CARE UNDE F INE D
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 8
Publication Date: SEP. 2001 Revision:A
tm
TE CH
T15V256A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to DIN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5pF. guaranteed but not 100% tested. This parameter is
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP .
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 9
Publication Date: SEP. 2001 Revision:A
tm
TE CH
T15V256A
PACKAGE DIMENSIONS 28-LEAD SOP
e1 28 15
E HE
Detail F 1 D A2 S y Seating Plane Symbol A A1 A2 b C D E e HE L LE S y Dimension in inches min. 0.01 0.083 0.014 0.004 0.322 0.044 0.453 0.026 0.047 0 typ. 0.085 0.016 0.006 0.713 0.331 0.050 0.465 0.033 0.059 39 max 0.098 0.087 0.018 0.008 0.733 0.338 0.056 0.476 0.041 0.071 0.005 10 Dimension in mm min. 0.25 2.13 0.39 0.1 8.2 1.12 11.5 0.65 1.2 0 typ. 2.15 0.4 0.15 18.1 8.4 1.27 11.8 0.85 1.5 1.0 max. 2.5 2.17 0.41 0.2 18.6 8.6 1.42 12.1 1.05 1.8 0.12 10 Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec. e A1 See Detail F A LE b 14 L e1 C
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 10
Publication Date: SEP. 2001 Revision:A
tm
TE CH
T15V256A
PACKAGE DIMENSIONS 28-LEAD TSOP-I FORWARD AND REVERSE
D
(8X13.4mm)
C 1 28 b E e 14 15 A2 "A" A A1 Seating plane y
Db Gauge plane Seating plane L
0.010
Detail "A"
L1
SYMBOL A A1 A2 b c Db E e D L L1 y
DIMENSIONS IN INCHES 0.047(max.) 0.0040.002 0.0390.002 0.008(typ.) 0.006(typ.) 0.4650.004 0.3150.004 0.022(typ.) 0.5280.008 0.0200.004 0.03150.004 0.004(max.) 0 ~5
P. 11
DIMENSIONS IN MM 1.20(max.) 0.100.05 1.000.05 0.20(typ.) 0.15(typ.) 11.800.10 8.000.10 0.55(typ.) 13.400.20 0.500.10 0.800.10 0.10(max.) 0 ~5
Publication Date: SEP. 2001 Revision:A
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.

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